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Verilog® HDL: A Guide to Digital Design and Synthesis

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Verilog® HDL: A Guide to Digital Design and Synthesis,
Second Edition
By Samir Palnitkar

Table of Contents

Part 1. Basic Verilog Topics

Chapter 1. Overview of Digital Design with Verilog HDL

Chapter 2. Hierarchical Modeling Concepts

Chapter 3. Basic Concepts

Chapter 4. Modules and Ports

Chapter 5. Gate-Level Modeling

Chapter 6. Dataflow Modeling

Chapter 7. Behavioral Modeling

Chapter 8. Tasks and Functions

Chapter 9. Useful Modeling Techniques

Part 2. Advanced VerilogTopics

Chapter 10. Timing and Delays

Chapter 11. Switch-Level Modeling

Chapter 12. User-Defined Primitives

Chapter 13. Programming Language Interface

Chapter 14. Logic Synthesis with Verilog HDL

Chapter 15. Advanced Verification Techniques

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