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Verilog®-XL Reference

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Verilog®-XL Reference
Product Version 5.81
June 2006

Table of Contents

1 Introduction

2 Lexical Conventions

3 Data Types

4 Expressions

5 Assignments

6 Gate and Switch Level Modeling

7 User-Defined Primitives (UDPs)

8 Behavioral Modeling

9 Tasks and Functions

10 Disabling of Named Blocks and Tasks

11 Hierarchical Structures

12 Using Specify Blocks and Path Delays

13 Timing Checks

14 System Tasks and Functions

15 Programmable Logic Arrays

16 Interconnect Delays

17 Timescales

18 Delay Mode Selection

19 The Behavior Profiler

20 The Value Change Dump File

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