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IEEE Standard Verilog Hardware Description Language IEEE Computer Society

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IEEE Standard Verilog Hardware
Description Language
IEEE Computer Society
Sponsored by the
Design Automation Standards Committee

Table of Contents

1 Lexical conventions

2 Data types

3 Expressions

4 Scheduling semantics

5 Assignments

6 Gate and switch level modeling

7 User-defined primitives (UDPs)

8 Behavioral modeling

9 Tasks and functions

10 Disabling of named blocks and tasks

12 Hierarchical structures

13 Configuring the contents of a design

14 Specify blocks

15 Timing checks

16 Backannotation using the Standard Delay Format (SDF)

17 System tasks and functions

18 Value change dump (VCD) files

19 Compiler directives

20 PLI overview

21 PLI TF and ACC interface mechanism

22 Using ACC routines

23 ACC routine definitions

24 Using TF routines

25 TF routine definitions

26 Using VPI routines

27 VPI routine definitions

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