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1 A Tutorial Introduction
2 Logic Synthesis
3 Behavioral Modeling
4 Concurrent Processes
5 Module Hierarchy
6 Logic Level Modeling
7 Cycle-Accurate Specification
8 Advanced Timing
9 User-Defined Primitives
10 Switch Level Modeling
11 Projects
The Verilog® Hardware Description Language,
Fifth Edition
Donald E. Thomas
Philip R. Moorby
Fifth Edition
Donald E. Thomas
Philip R. Moorby
Table of Contents
2 Logic Synthesis
3 Behavioral Modeling
4 Concurrent Processes
5 Module Hierarchy
6 Logic Level Modeling
7 Cycle-Accurate Specification
8 Advanced Timing
9 User-Defined Primitives
10 Switch Level Modeling
11 Projects
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