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1. INTRODUCTION TO VERILOG HDL
2. DATA TYPES IN VERILOG
3. ABSTRACTION LEVELS IN VERILOG: BEHAVIORAL, RTL, AND STRUCTURAL
4. SEMANTIC MODEL FOR VERILOG HDL
5. BEHAVIORAL MODELING
6. RTL AND STRUCTURAL MODELING
7. MIXED STRUCTURAL, RTL, AND BEHAVIORAL DESIGN
8. SYSTEM TASKS AND FUNCTIONS
9. COMPILER DIRECTIVES
10. INTERACTIVE SIMULATION AND DEBUGGING
11. SYSTEM EXAMPLES
12. SYNTHESIS WITH VERILOG
13. VERILOG SUBSET FOR LOGIC SYNTHESIS
14. SPECIAL CONSIDERATIONS IN SYNTHESIZING VERILOG
15. SPECIFY BLOCKS — TIMING DESCRIPTIONS
16. PROGRAMMING LANGUAGE INTERFACE
17. STRENGTH MODELING WITH TRANSISTORS
18. STANDARD DELAY FORMAT
19. VERILOG-A AND VERILOG-MS
20. SIMULATION SPEEDUP TECHNIQUES
THE COMPLETE VERILOG BOOK
by
Vivek Sagdeo
by
Vivek Sagdeo
Table of Contents
2. DATA TYPES IN VERILOG
3. ABSTRACTION LEVELS IN VERILOG: BEHAVIORAL, RTL, AND STRUCTURAL
4. SEMANTIC MODEL FOR VERILOG HDL
5. BEHAVIORAL MODELING
6. RTL AND STRUCTURAL MODELING
7. MIXED STRUCTURAL, RTL, AND BEHAVIORAL DESIGN
8. SYSTEM TASKS AND FUNCTIONS
9. COMPILER DIRECTIVES
10. INTERACTIVE SIMULATION AND DEBUGGING
11. SYSTEM EXAMPLES
12. SYNTHESIS WITH VERILOG
13. VERILOG SUBSET FOR LOGIC SYNTHESIS
14. SPECIAL CONSIDERATIONS IN SYNTHESIZING VERILOG
15. SPECIFY BLOCKS — TIMING DESCRIPTIONS
16. PROGRAMMING LANGUAGE INTERFACE
17. STRENGTH MODELING WITH TRANSISTORS
18. STANDARD DELAY FORMAT
19. VERILOG-A AND VERILOG-MS
20. SIMULATION SPEEDUP TECHNIQUES
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