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Design Through Verilog HDL

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Design Through Verilog HDL
T. R. Padmanabhan
B. Bala Tripura Sundari

Table of Contents

1 INTRODUCTION TO VLSI DESIGN

2 INTRODUCTION TO VERILOG

3 LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG

4 GATE LEVEL MODELING – 1

5 GATE LEVEL MODELING – 2

6 MODELING AT DATA FLOW LEVEL

7 BEHAVIORAL MODELING — 1

8 BEHAVIORAL MODELING — 2

9 FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES

10 SWITCH LEVEL MODELING

11 SYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES

12 QUEUES, PLAS, AND FSMS

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